Pulse width modulation of a signal or power source involves the modulation of its duty cycle to either convey information over a communications channel or control the amount of power sent to a load. To obtain high resolution in the duty cycle and more efficient power consumption for the load, typical solutions require a high resolution and high frequency PWM signal with a low input clock frequency.
U.S. Pat. No. 6,765,422 (e.g., Aslan et al.) describes the basic technology and is all herein incorporated by reference in their entirety for all purposes. More particularly, FIG. 1 illustrates a block diagram for obtaining a finer resolution using an error integrating loop 100. For example, the error integrating loop 100 may be used to achieve a target PWM duty cycle of 50.39% which is equal to 8.0625/16 using a 360 KHz clock. This would result in the frequency of PWM signal at 22.5 KHz, i.e., 360 KHz/16 clock cycles per single PWM cycle.
To achieve the target PWM duty cycle of 50.39%, 8 clock cycles long PWM pulse signals and a 9 clock cycle long PWM pulse signal are selectively generated for a PWM period. In FIG. 1, a current PWM signal 104 is subtracted by the target PWM pulse clock cycles 102, i.e., 8.0625, to generate a current error 106. The current error 106 is added to an accumulated error 108 to generate the next stage of the accumulated error 108. The accumulated error 108 is then compared with a reference value (e.g., zero) using a comparator 112. If the accumulated error 108 is greater than or equal to zero, the comparator 112 generates a signal 114 which triggers a two-to-one MUX 116 to select an 8 clock cycle long pulse signal 118 as the current PWM signal 104. If the accumulated error 108 is less than zero, a 9 clock cycle long pulse signal 120 is selected as the current PWM signal 104. In addition, the current PWM signal 104 may be forwarded to a load 122, such as a fan control device.
FIG. 2A is a table 200 illustrating 32 PWM cycles of the error integrating loop 100 of FIG. 1. As illustrated in FIG. 2A, each of the 2nd PWM cycle and the 18th PWM cycle is a 9 clock cycle long pulse, whereas each of the remaining PWM cycles is an 8 clock cycle long pulse. Moreover, the period of the PWM signal is 16 PWM cycles, and its duty cycle is {(8*15)+9}/16*16=50.39%. Although the error integrating loop 100 generates the PWM signal which achieves the target PWM duty cycle, the fixed location of the 9 clock cycle long pulse within the PWM period as illustrated in FIG. 2B may create noise audible to human ears, thus impeding the efforts of realizing a silent fan control.